(1) Field of the Invention
The present invention relates to a static memory device, and more particularly to a high stability static memory device having metal-oxide-semiconductor field-effect transistors (hereinafter referred to as "MOSFETs").
(2) Description of the Related Art
Generally, how a flip-flop is designed for static memory device determines good or bad of a product it is The most important concern in designing a flip-flop relates to the stability of the memory. The IEEE Journal of Solid-State Circuits, Vol. Sc-22, No. 5, October, 1987, discusses the stability of a memory cell by comparing a static memory cell in which the flip-flop is formed by CMOS inverters and a static memory cell in which the flip-flop is constituted by inverters with resistor loads. As discussed therein, the most effective and assured way for enhancing such stability is to increase the so-called "cell ratio".
Herein the relation between the cell ratio and the stability of the cell is explained with reference to the drawings.
FIG. 1 shows a bit line load circuit and a memory cell circuit for a typical static memory device. In the drawings, D, D denote a pair of bit lines; W denotes a word line; Q1, Q2 denote driver MOSFETs of inverters constituting a flip-flop of the memory; Q3, Q4 denote access MOSFETs for connecting the memory cell with the bit lines D, D; R1 and R2 denote load resistors of the inverters of the flip-flop for the memory; and Q5, Q6 denote load MOSFETs of the bit lines D, D. Here, it is assumed that the MOSFETs constituting the memory cell are all N-channel MOSFETs and the load MOSFETs of the bit lines are both P-channel MOSFETs.
The operation of the above circuit is briefly explained hereunder.
When data are written to the memory cell, the data to be written are sent to the bit lines from a write circuit (omitted in FIG. 1) and one of the bit lines is raised to a V.sub.CC level and the other becomes approximately a GND level. For example, when the opposite level data are to be written to the memory cell in which a node A is a high level (hereinafter referred to as "H-level") and a node B is a low level (hereinafter referred to as "L-level"), the word line W is caused to be in a selecting state (the V.sub.CC level) with the bit line D being approximately at GND level and the bit line D being at the V.sub.CC level. Then, the level of the node A which is H-level will be discharged through the access MOSFET Q3 so that the level of the node A will be turned to the L-level. Consequently, the driver MOSFET Q2 will be OFF, and the H-level of the bit line D enters into the node B through the other access MOSFET Q4. In this manner, the opposite level data with respect to the initial data can be written in the memory cell.
Immediately after the writing of the data, the H-level of the memory cell is at a voltage lower than the V.sub.CC by a threshold voltage V.sub.T of the access MOSFET. When the writing is completed, the word line W becomes the L-level and the memory cell is then in a holding state. Under this state, both the access MOSFETs Q3 and Q4 are OFF, the driver MOSFET Q1 is ON and the driver MOSFET Q2 is OFF. Each of the load resistors R1 and R2 of the cell used has a high resistance value of above 100 G.OMEGA. so that the L-level of the memory cell becomes approximately the GND level. On the other hand, although the H-level of the memory cell is at a voltage lower than the V.sub.CC by the threshold voltage V.sub.T of the access MOSFET immediately after the writing of the data as already explained, there develops a gradual charging through the cell load resistor, so that the H-level of the memory cell eventually reaches the V.sub.CC level. Thus, in the data holding state in which once a sufficient time has passed after the data writing, the L- and H-levels of the cell are the GND level and the V.sub.CC level, respectively.
Next, the read-out operation is explained. In the read out operation, the word line is selected normally in a state in which the bit lines have been precharged. That is, before the word line becomes the H-level, the potential of the bit lines D, D has already raised to the V.sub.CC level. Therefore, when the level of the word line gradually rises, first the access MOSFET connected to the node at the L-level side of the memory cell becomes ON and, thus, the potential of the L-level of the memory cell starts to rise. However, under the normal state, this level is lowered by the driver MOSFET in an ON-state, followed by the lowering of the level of the word line in a precharged state down to the neighborhood of the GND level. On the other hand, the bit line at the node of the H-level side remains at a precharged state without being discharged to the L-level. That is, the data held by the memory cell has been thus read-out to the bit lines.
In performing the data read-out operation, an important factor for determining the stability of the memory cell is the degree as to how high the L-level at the L-level side node rises. If the L-level exceeds a threshold voltage of the driver MOSFET, the H-level of the memory cell abruptly drops from the V.sub.CC level to a voltage lower by the threshold voltage of the access MOSFET than the voltage of the word line. This results in the reduction of a potential difference between the H-level and the L-level of the memory cell and, in an actual memory cell, there is a risk in which the H-level and the L-level of the memory cell is reversed. In order to prevent the levels of the memory cell from being reversed, it is necessary to limit the rising of the L-level of the memory cell (which means that the rising of the L-level of the memory cell be limited so as not to exceed the threshold voltage of the driver MOSFET).
Next, how the L-level of the memory cell results is explained with reference to FIGS. 2 and 3.
FIG. 2 is an equivalent circuit diagram showing a portion of the circuit shown in FIG. 1. A transistor Q30 in FIG. 2 corresponds to the load transistors Q5, Q6 of FIG. 1; a transistor Q20 in FIG. 2 corresponds to the transistors Q3, Q4 of FIG. 1; a transistor Q10 in FIG. 2 corresponds to the driver transistors Q1, Q2 of FIG. 1; and a resistor R in FIG. 2 corresponds to the load resistors R1, R2 of FIG. 1, respectively.
Now, in FIG. 1, if the potential of the word line W rises and reaches the V.sub.CC level when the node A is at the L-level and the node B is at the H-level, the level of the node A equals the level of the node A under the state in which the V.sub.CC is applied to the gate electrode (node B) of the transistor Q10 in FIG. 2. Here, the circuit of FIG. 2 can be considered as an inverter circuit which is constituted by the transistor Q10 used as a driver MOSFET and a parallel circuit of the two MOSFETs Q20 and Q30 connected in series and the resistor R used as a load element. Input/output characteristics of such inverter are shown in FIG. 3. FIG. 3 shows variations in the input/output characteristics when the ratios between the current supply capability of the transistor Q10 and that of the transistor Q20 (generally and simply referred to as "cell ratio") are used as parameters, and this shows that the current supply capability of the transistor Q10 is two times, three times and four times greater than that of the transistor Q20. It can be appreciated from this that the greater the cell ration is, the lower are the output voltages with respect to the same input voltage.
Thus, in order to ensure a high stability of the memory cell, it is necessary to increase the current supply ratio between the driver MOSFET and the access MOSFET so that, when the level of the word line rises, the L-level of the memory cell does not go high.
As a constant for expressing the current supply capability of the MOSFETs, the gain coefficient .beta. is used. This gain coefficient .beta. derives from the product of the process gain coefficient K determined mainly by process variations and the aspect ratio (W/L, W and L being the width and the length of the gate, respectively) of the gate of the MOSFET. This is given by: EQU .beta.=K.W/L.
Also, the cell ratio r is given by the ratio between the gain coefficient .beta..sub.D of the driver MOSFET and the gain coefficient .beta..sub.A of the access MOSFET. This is: EQU r=.beta..sub.D /.beta..sub.A.
According to the conventional technique, the means for making the cell ratio large has been to increase the aspect ratio (W/L) of the driver MOSFET and to decrease that of the access MOSFET. In other words, the gate width of the driver MOSFET is made large and the gate length thereof is made short while the gate width of the access MOSFET is made small and the gate length thereof is made long.
Thus, according to the conventional techniques referred to above, it has been the practice that (1) either the gate width of the driver MOSFET is made large or the gate length of the access MOSFET is made long and that (2) either the gate length of the driver MOSFET is made short or the gate width of the access MOSFET is made small. However, if this technique is attempted to be further advanced, the problem that the former faces is an increase in the chip size involved and the problem that the latter faces is an increase in process variations which cause the lowering of breakdown voltage and the operational instability as well as the lowering of production yields to a large extent. Thus, today, it is considered that neither the practice (1) nor the practice (2) above can help producing a desirable result if used along the line of the conventional technology.